Post-Si High Volume Debug Engineer

Location: San Diego, California
Date Posted: 01-22-2018
The Validation Team is part of the central SoC digital hardware organization responsible for the overall quality of the SoC silicon. This team works closely with architects, designers, verification engineers, software engineers, and customers. The team is currently seeking a candidate for the position of Electrical Failure Analysis engineer. In this role, you will work on debugging the failing systems (from the internal testing or customer returns), understand the root cause and implement corrective actions through design and test enhancements. You will also work on the automation of failure analysis techniques, so tests can narrow down the failure to a specific circuit or function.
Minimum Qualifications:
Candidate will have five or more years of experience working in silicon environment in SoC debug using JTAG Debuggers, basic understanding of power performance, Vmin, Fmax methodology, hands-on experience with lab equipment such as scopes, logic analyzers, etc. Experience of doing PVT and regression is a must. Strong C and Python programming skills.
Preferred Qualifications:
8-12 years industry experience, Strong SoC silicon debug background solving hardware and software problems. Solid experience in post-silicon enabling and bring-up. Strong C or Python/Perl scripting experience, including tool creation and flow automation. Using lab equipment (scope and protocol analyzer).
Required: Bachelor's, Electrical Engineering
Preferred: Master's, Electrical Engineering or equivalent experience
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