Digital Design Verification Engineers for Mixed-Signal ASICs

Location: San Diego, California
Date Posted: 02-02-2018
Job Overview:
Successful applicants will be responsible for participating in, or leading, the verification of state-of-the-art ASICs in advanced digital deep sub-micron CMOS processes for multi-function mobile platforms.

Responsibilities will include all, or some, of the following:
  • Verification of chip level functionality (mainly connectivity, programmability, power up/down, mode control, reset).
  • Negotiating and executing functional verification plans.
  • Writing/debugging/maintaining behavioral models, monitors, and self-checking test benches.
  • Logging bugs and tracking verification results.
  • Delivering status reports and verification reviews.
  • Generating and maintaining verification schedules.

 Minimum Qualifications:
Applicants should have a minimum of 5 years of digital verification experience including all, or some, of the following:
  • Detailed knowledge of self-checking test bench architectures (including directed and random-constrained generation) and coverage-driven verification techniques at the functional, assertion and code levels.
  • Working knowledge of Object-Oriented SystemVerilog principles including experience with VMM, OVM, or UVM.
Preferred Qualifications:
Please see minimum qualifications.
Please see minimum qualifications.
Technical Recruiter
Novus Resources  

this job portal is powered by CATS