Physical Design Engineer

Location: Raleigh, North Carolina
Date Posted: 02-03-2018
Job Overview:
Team is responsible for delivering physical implementations of high speed custom processors for server and mobile applications. This position is for floorplanning/place and route, power grid and clock tree design and analysis; core level timing; signal integrity closure; extraction; DRC and LVS. The engineer will need to use semi-custom layout where appropriate to maximize density, performance, and power efficiency. Implement DFM and DFT requirements.

Minimum Qualifications:
10+ years of experience in physical design of:
  • Floorplaning
  • Power Grid Design
  • Place and Route
  • Static Timing Analysis
  • Physical Verification Cadence/Synopsys/Mentor EDA CAD tool
  • Advanced technology experience in 10nm, 14/16nm, and FinFet

Preferred Qualifications:
The candidate should be able to work with a team of engineers on all aspects of Physical Design tasks on ASIC solutions in next generation technologies. Responsibilities include: Floor Planning, Clock Tree Design, Place and Route, PDN, Timing analysis and closure. Perform various physical verification checks (such as LVS, DRC, design-for-manufacturing & design-for-yield) at the chip and block levels. Manage schedules and support cross-functional engineering effort to drive to signoff closure for tapeout.

Required: Bachelor's, Electrical Engineering or equivalent experience
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