Digital Verification Engineer

Location: San Diego, California
Date Posted: 02-05-2018
Job Overview:
Currently seeking digital verification engineers for the mixed-signal ASICs that support mobile platforms for next generation RFIC/PMIC/Codec technologies. Successful candidates will be working on the following: Block/Subsystem/SoC level digital IP verification using constraint-random coverage methodologies at both RTL and Gate Level. The skills involved includes SV/UVM/UVM_REG/Randomization/Coverage/SVA.

Minimum Qualifications:
  • Minimum Bachelors degree in Electrical Engineering or Computer Engineering
  • Three years minimum experience and working knowledge of Object-Oriented SystemVerilog principles using UVM/OVM/VMM methodologies.

Preferred Qualifications:
  • Extensive hands on experience in verifying digital blocks, building UVM based TB, writing UVM sequences, constraint-random testcases, using regModel (UVM_REG) API, drivers, monitors, scoreboard, functional coverage (covergroups), assertions (SVA), simulations, regression, debug, bug reporting/tracking.
  • Experience in debugging RTL & Gate level simulations.
  • Part of multiple tapeouts with high quality verification.

Required: Bachelor's, Electrical Engineering
Preferred: Master's, Electrical Engineering or equivalent experience

Technical Recruiter
Novus Resources  

this job portal is powered by CATS