Synth/STA Engineer

Location: San Jose, California
Date Posted: 02-05-2018
Job Overview:
You will be a part of an organization responsible for development of SoC designs. You will be also involved in the timing constraint development, synthesis, DFT of sub-systems, logic equivalency checks, and static low power checks for isolation and level shifter implementations. You will be also involved in the timing constraint development, synthesis and DFT of sub-systems, logic equivalency checks, static low power checks for isolation and level shifter implementations. You will be responsible for reviews related to timing constraints, synthesis results, timing results the team. You will be also involved in the static timing analysis of sub-systems and full chip on pre-route and post-route databases and drive timing closure of the subsystem and fullchip.

Minimum Qualifications:
Five years of industry experience in Synthesis, STA and Timing Closure

Education:
Required: Bachelors in Electrical/Computer Engineering
Preferred: Masters in Electrical/Computer Engineering

 
Technical Recruiter
Novus Resources
resumes@novus-resources.com  


 
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