Physical Design Engineer

Location: San Diego, California
Date Posted: 02-26-2018
Job Overview:
We are looking for a candidate to do Floor planning, P&R, timing closure SI prevention/fixing, power planning, CTS, PV and I/R drop for Block as well as Top level MSM. Work on PD projects.
Minimum Qualifications:
Must be able to deal with MSM Top level complexity from FP, Placement, CTS, Routing and timing closure. Must be able to take the Hardmacro through P&R from Netlist to GDS including timing closure, formal and Physical verification.
Tools: EDA Physical design tools experience ( Examples: Cadence Innovas, Synopsys ICC2, PrimetimeSi/Calibre/ etc)
Skills: Physical design implementation expertise in latest technology nodes in one of the below domains or all of these:
  • Floorplanning at Full chip level or Macro or Block Level
  • Macro placement, power grid implementation, power routing, special routing like analog signals etc
  • Power collapse/Low power implementation flow
  • P&R: Place and route at chip level or block level, perform placement, timing closure in P&R mode, perform clock tree synthesis , routing etc.
  • Timing closure/STA a.Perform STA using primetimeSi or Tempus or any industry standard STA engine, timing closure, ECO generation, timing correlation
  • Deep understanding of timing skills to perform correlation, timing fixes , corner/voltage definetions etc.
  • Clock Tree Synthesis:
  • Perform custom or regular clock tree implementation at block level or top level.
  • Clock tree balance of complicated tree, clock power reduction techniques etc.
  • Low Power Implementation
  • Power collapse/power gaing techniques/implementation
  • UPF/CPF flow knowledge
  • CLP/F
  • Physical Verification Using Calibre
  • Running all the PV checks (DRc/LVS/ERC/Softcheck ) and deep understanding of all the rules and fixes
  • Perl/Python/Shell script experience is also preferred to help with automation 
Preferred Qualifications:
Please see minimum qualifications.
Required: Bachelor's, Computer Engineering
Preferred: Master's, Computer Engineering
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