Sr. Engineer

Location: San Diego, California
Date Posted: 03-02-2018
Job Overview:
Mixed signal transistor level circuit design & simulations of I/O circuitry for IO pads (GPIO, Custom I/O, Specialty I/O). Work with layout, packaging and system engineers to meet design specifications. Work closely with modeling & characterization team to provide front & back end models for their design.
Minimum Qualifications:
Proven track record of mixed-signal transistor level circuit design in the field of I/Os. Recent experience in I/O designs for wireless devices including Low-Power I/O design. Solid understanding of related CMOS process technology issues, including FinFET. Experience in Cadence Tool (eg, Virtuoso, Spectre) 4-8 yrs experience.
Preferred Qualifications:
  • Familiar with Power & Signal Integrity and understanding of signal switching, noise & design issues.
  • Familiar with I/O design methodology & flow, Calibration, JTAG design requirements, understanding of analog circuitry.
  • Familiarity with ASIC flow: Synopsys libraries, LEF, CPF, UPF, Place & Route & understanding of top level verification flow.
  • Familiarity with package/board constraints is a plus.
  • Familiarity with FinFET is a plus.
Required: Bachelor's in Electrical or Computer Engineering
Preferred: Master's in Electrical or Computer Engineering
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