Static Timing Analysis Engineer

Location: Various Cities, United States
Date Posted: 04-09-2018
Summary of Role:  Our Client is looking for an experienced Static Timing Analysis Engineer with experience using industry-standard processes and tools.

(Locations:  Raleigh, NC; Rochester, MN; Austin, TX; Burlington, VT)
Essential Responsibilities:  
·         Knowledge of Static Timing Analysis (STA) in recent semiconductor technology nodes (22nm, 14 nm, 7nm, and beyond).
·         Knowledge of SDC timing constraints, and running STA in a MMMC (multi-mode, multi-corner) environment.
·         Experience in transistor and gate-level static timing and noise analysis.
·         Clocking skills (needs clocking architecture knowledge).
·         Knowledge of place-and-route and ability to guide Physical Design team to ensure Design closure.
·         Knowledge of industry Computer-Aided Design (CAD) tools such as Cadence and Synopsys.
·         Ability to use scripting languages to automate process flow.
·         Work effectively with global team and be self-motivated to solve problems.
·         Manage deliverables.
·         Communicate clearly both verbally and in writing.
·         Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety & Security requirements and programs
Required Qualifications
  • Bachelor’s in Electrical Engineering, plus 11 or more years of experience.
  • Fluent in English Language – written & verbal.
  • Experience with Cadence, Synopsys and/or Mentor tools.
Preferred Qualifications:
  • Master’s Degree in Electrical Engineering, plus 8 or more years of experience.
  • Experience working with communications chips.
  • Familiarity with industry standard interfaces.
An offer of employment with our Client is conditioned upon the successful completion of a background check & drug screen, as applicable and subject to applicable laws and regulations.
Technical Recruiter
Novus Resources  

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