Physical Design Engineer

Location: Various Locations, United States
Date Posted: 07-17-2018
Position Title:   Physical Design Engineer
Work Area:  World Wide Design Center
Location: Santa Clara ,CA ; Burlington ,VT ; Raleigh NC ; Rochester, MN ; Austin, TX
Essential Responsibilities:         
  • Must have experience in completing PD tasks on recent Technologies.
  • PD skill: RLM and Top Level experience required.
  • Needs clocking architecture knowledge.
  • Clocking skills (knowledge of Physical Routing tools plus Timing implications).
  • Ability to use scripting languages to automate process flow.
  • Will work directly with Timing Team to ensure Design closure.
  • Work effectively with global team and be self-motivated to solve problems.  Manage deliverable.
  • Communicate clearly both verbally and in writing.
  • Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety & Security requirements and programs

Required Qualifications: 
  • Bachelor’s in Electrical Engineering plus 10 or more years of experience.
  • Language Fluency – Fluent in English Language – written & verbal.
EDA tools (Cadence, Synopsys, Mentor tools): 
  • Design Compiler (DC-topo), StarRC, PrimeTime, Cadence SoC Encounter, IC Compiler (ICC), Formality, DFT Compiler, UPF, Mentor Calibre, Cadence Virtuoso.
  • Scripting Languages: Tcl, Cshell, Makefile.
HDL language: VHDL and Verilog.‚Äč

Design Implementations: 
  • Block level timing constraints and IP constraints integration.
  • Logic synthesis & Clock gating insertion using DC/DCT.
  • Floorplaning using ICC/Innovus.
  • Powergrid generation script using Astro.
  • Clock Tree Synthesis (CTS) and Place and Route (P&R) using ICC2.
  • Timing closure, ECO process using PrimeTime DMSA and ICC2.
Preferred Qualifications:
  • Master’s Degree in Electrical Engineering
  • Experience working with communications chips.
  • Familiarity with industry standard interfaces.
Technical Recruiter
Novus Resources  

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