DFT Engineer

Location: San Diego, California
Date Posted: 05-17-2018
Job Overview:
DFT Engineer position will be responsible for implementing advanced DFT/DFD/DFM (design for test/debug/manufacturability) techniques for high performance CPU. The position will involve test insertion, vector development and validation and silicon debug.
 
Minimum Qualifications:
5 years experience in the following areas:
  • DFT/DFD/DFM techniques for complex SoCs.
  • Fault modeling Stuck-at, Transition, Path Delay, IDDQ, and other models.
  • Scan Insertion, ATPG, Scan Compression, At-speed Testing.
  • Scan Insertion using DFTCompiler or equivalent.
  • Exposure to industry standard ATPG tools like Mentor TestKompress, Synopsys TetraMax, Cadence Encounter Test.
  • Industry standard simulation tools such as VCS, Questasim, NCVerilog.
  • Scripting in Perl and Tcl -Exposure to SoC design and test for mobile market applications.
 
Preferred Qualifications:
Experience with:
  • LVmemBIST or Synopsys STAR BIST.
  • Silicon bring-up, debug, and validation of DFT features on ATE.
  • Implementation of DFT/DFD/DFM techniques for high performance CPU.
  • Work with design teams to improve low coverage on designs to desired target.
  • Generate ATE patterns and work with Test Engineers during pattern bring up and debug.
 
Education:
Required: Bachelor's, Electrical Engineering
Preferred: Master's, Electrical Engineering or equivalent experience
 
Technical Recruiter
Novus Resources
resumes@novus-resources.com  


 
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