DDR PHY Timing Engineer

Location: San Diego, California
Date Posted: 07-17-2018
Job Overview:
This position requires involvement in all aspects of front-end and physical design, guiding a cross-functional DDR PHY team on timing considerations from architecture through tapeout. Specific responsibilities may include:
  • Identification and analysis of design timing bottlenecks and mitigation solutions.
  • Guidance to front-end and physical teams on all aspects of timing considerations.
  • Development and support of PrimeTime STA timing constraints.
  • Execution of Star-RCXT/PrimeTime flow for analysis and sign-off.
  • Development of system timing budget and application to internal constraints.
  • Development of scripted automation for efficient data and waiver processing.
Minimum Qualifications:
Practical experience with static timing analysis(STA) and PrimeTime constraints development. Relevant skillset:
1. VLSI circuits understanding, including Spice analysis.
2. DDR operation and timing considerations.
3. Unix/Perl/TCL scripting (must be comfortable with writing scripts).
Preferred Qualifications:
Excellent communication skills and ability to work efficiently with a global cross-functional team.
Required: Bachelor's, Electrical Engineering
Preferred: Master's, Electrical Engineering
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