Design Verification Engineer

Location: Irvine, California
Date Posted: 07-17-2018
Job Overview:
Perform design verification of GNSS location cores and IP. Develop and write system verilog based tests using UVM. Debug RTL issues and provide feedback to designers. Provide support to SOC DV team during GNSS integration to SOC. Implement and debug Gate Level and Power Aware simulations. Work alongside other DV and design engineers for test planning and test implementation.
Minimum Qualifications:
  • Minimum 5 years experience focused in design verification work.
  • Experience in verilog, systemverilog and UVM based test implementation.
  • Experience in debugging RTL.
  • Experience with the latest verification tools such as Synopsys VCS, Modelsim, Cadence, etc.
  • Be able to implement UVM agents and sequences. Good communication skills.
Preferred Qualifications:
10 years experience focused in design verification is preferred. Have implemented a UVM verification environment from the ground up and  a background in hardware design.
Required: Bachelor's, Computer Engineering

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