Synthesis/STA Engineer

Location: San Jose, CA
Date Posted: 05-06-2016
NOVUS is seeking a Synthesis/STA Engineer to be apart of our world class client located in San Jose, CA.  You will be join the organization responsible for development of SoC designs. You will be involved in the integration of various SoC designs and perform various Lint checks. You will be also responsible for performing CDC checks at sub-system level and chip level and work with the team to address CDC issues. You will be also involved in the timing constraint development, synthesis, DFT of sub-systems, logic equivalency checks, and static low power checks for isolation and level shifter implementations. You will be responsible for RTL integration of various SoC designs, perform various Lint checks to make sure coding guidelines are met for proper synthesizable RTL, RTL compatible for DFT, and low power. You will be also responsible for CDC checks at sub-system level and chip level. You will also work with the team to address any CDC issues. You will be also involved in the timing constraint development, synthesis and DFT of sub-systems, logic equivalency checks, static low power checks for isolation and level shifter implementations. You will be responsible for reviews related to CDC constraints, timing constraints, synthesis results, DFT coverage results with the team. You will provide feedback to designers of any Lint, CDC, DFT, synthesis, low power, and timing issues that need to be addressed. You will be also involved in the static timing analysis of sub-systems and full chip on pre-route and post-route databases. You will be responsible for power analysis using tools like Power Artist and Prime Power for sub-systems and entire chip by working with the lead engineer. Lastly you will make regular contributions to the overall improvement in design methodology to drive productivity and quality of result.


7 years of experience with Verilog ASIC design and ASIC implementation related to post-RTL activities. Knowledge about multi-domain clock synchronization is required. Experience with design checks like Lint, and CDC is required. Experience with Power Artist and Prime Power tools for power analysis is preferred. Experience with Synopsys tools for ASIC synthesis, DFT and static timing analysis is a must. Experience with Logic equivalency checks is a must. Experience with static low power checks is preferred. Experience with full-chip static timing analysis through tapeout is a plus. Must have worked on at atleast one SoC design with direct participation in RTL integration, Lint checks, CDC checks, timing constraints, synthesis, and DFT. Experience with memory bist insertion and simulations is a plus. Innovative, self-directed and self-motivated team player able to thrive in a fast-paced, organic engineering environment. Experience with developing, tracking, and achieving project schedules. Good verbal and written communication skills.


Exposure to System Verilog, Perl/Tcl/Makefile scripting


Required: Bachelor's, Computer Engineering and/or Electrical Engineering or equivalent experience Preferred: Master's, Computer Engineering and/or Electrical Engineering or equivalent experience
Technical Recruiter
Novus Resources
resumes@novus-resources.com  


 
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