Synthesis / STA Engineer

Location: San Jose, CA
Date Posted: 05-06-2016
NOVUS is accepting applications for Synthesis /STA Engineer to perform synthesis, DFT insertion, low-power checks, logic equivalency checks, static timing analysis and power analysis on digital blocks. This position is located in San Jose, CA with our Fortune 500 client ranked #2 by Forbes as the world’s most admired company.
  • Timing constraint development, synthesis and DFT insertion for sub-systems, logic equivalency checks, static low power checks for isolation and level shifter implementations and power analysis.
  • Reviews related to timing constraints, synthesis results, DFT coverage results with the team.
  • Provide feedback to designers of any DFT, Synthesis, Low Power, Timing issues that need to be addressed.
  • Static Timing Analysis of sub-systems and full chip on pre-route and post-route databases.
Minimum Qualifications:
  • Synopsys tools for ASIC synthesis, DFT and Static Timing Analysis
  • Logic equivalency checks
  • Static Low Power checks
  • Power analysis tools such as power artist or PTPX is a plus
  • Full-chip static timing analysis through tapeout is a plus.
 Preferred Qualifications:
  • Experience with Low Power formats (UPF/CPF) Low Power Implementation and Verification Experience with CLP
Bachelors/Masters in Electrical/Computer Engineering
Technical Recruiter
Novus Resources  

this job portal is powered by CATS