Verification Engineer

Location: Raleigh, North Carolina (NC)
Date Posted: 06-26-2016
Novus Resources has an immediate opening for a highly skilled veteran Verification Engineer to join our clients server team. The job entails working very closely with a high performance DDR and memory IP team to verify state of the art hardware IP. Candidate will be part of a DDR SS IP design and verification team. Candidate will verify a multi memory standard Memory Controller and/or multi memory PHY design. Provide working knowledge of UVM Architecture and develop UVM/System verilog components, tests, and test bench. Utilize industry standard tools to analyze simulation results, coverage results, and debug fails. Utilize industry standard VIP to ensure design adhere to JEDEC standards. The candidate will own verification of a hardware IP DDR/future memory controller and subsystem. The candidate should have knowledge of all JEDEC memory specs through DDR, nonvolatile solutions, and HBM as well as proprietary solutions such as HCM. The individual should be able to apply working knowledge of UVM Architecture and will develop UVM/System Verilog components and environments. The responsibilities include, but are not limited to UVM/SystemVerilog development, analysis of simulation results and coverage (code and functional) using industry standard tools, working with revision control and regression systems, providing feedback to team members with regard to progress and status. Communication and interacting with team members on a daily face to face basis. Development of functional coverage and analyzing said coverage using industry standard tools. 
 
Minimum Qualifications 
10+ years experience in the following areas required: 
 -Hardware Verification 
 -Object Oriented Programming 
 -Industry standard verification tools such as simulators/waveform viewers/coverage tools 
 -Verification of JEDEC based memories.  
 -8+ years experience in the following areas required: 
 -OVM/UVM experience  
 -System Verilog coverage 
 -Gate level simulation 
 -Scripting Languages  
 -Regression and automation  
 
 -1+ year experience in the following area required: 
 - Knowledge of System Verilog Assertion (SVA) and formal techniques  
 
Preferred Qualifications 
 DDR memory controller verification, DDR PHY verification, Denali DDR VIP knowledge, JEDEC memory standards knowledge 
Education Requirements Required: Bachelor's, Computer Engineering and/or Computer Science or equivalent experience Preferred: Master's, Computer Engineering and/or Computer Science or equivalent experience
 


 
Technical Recruiter
Novus Resources
resumes@novus-resources.com  


 
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