Physical Design Engineer - GREAT OPPORTUNITY

Location: Raleigh, North Carolina (NC)
Date Posted: 08-08-2016
This position is for floorplanning/place and route, power grid and clock tree design and analysis; core level timing; signal integrity closure; extraction; DRC and LVS. The engineer will need to use semi-custom layout where appropriate to maximize density, performance, and power efficiency. Implement DFM and DFT requirements.  The team is responsible for delivering physical implementations of high speed custom processors for server and mobile applications.

10+ years experience in physical design oFloorplaning oPower Grid Design oPlace and Route oStatic Timing Analysis oPhysical Verification Cadence/Synopsys/Mentor EDA CAD tool experience Advanced technology experience o10nm, 14/16nm oFinFet

The candidate should be able to work with a team of engineers on all aspects of Physical Design tasks on ASIC solutions in next generation technologies. Responsibilities include: Floor Planning, Clock Tree Design, Place and Route, PDN, Timing analysis and closure. Perform various physical verification checks (such as LVS, DRC, design-for-manufacturing & design-for-yield) at the chip and block levels. Manage schedules and support cross-functional engineering effort to drive to signoff closure for tapeout


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