SoC Verification Engineer

Location: Raleigh, North Carolina (NC)
Date Posted: 09-02-2016

Our customer's Design Center is currently seeking a qualified SOC Verification Engineer. This individual will be involved in verifying next generation, wireless modem SoC IP blocks. The verification environment will utilize industry-standard HVL, constrained-random, coverage-driven VMM/UVM methodology.

Strong verification skills. Strong skills in HVL coding (SystemVerilog). VHDL/Verilog programming experience. Experience with scripting languages (Perl, Python). Experience in Assertion-based verification/Formal verification. Familiarity with VMM/UVM verification methodologies. Experience in programming and modeling languages (C, C++, SystemC) desirable. Experience with ASIC design flow from RTL coding to synthesis desirable. Familiarity with AMBA buses desirable. Excellent oral and written communication skills. The Candidate will work as part of a team of ASIC/FPGA engineers to develop a SOC for an advanced wireless communications system. Responsibilities include: *Module level Testplan and Testbench development, *Writing module constrained randomized test suite, *RTL debug, *Coverage

Experience in wireless and/or DSP modem design and verification a strong plus

Required: Bachelor's, Computer Engineering and/or Electrical Engineering

Technical Recruiter
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