RF Mask Layout Designer

Location: San Jose, CA
Date Posted: 09-20-2016
Novus is in search of a Layout Designer who will be responsible for physical design of RF and Analog circuits in a fast paced environment. Minimum expectations include:
- Providing accurate schedules
- Meeting project milestone deadlines
- Full self-sufficiency in debugging complex verification failures
- Fully understanding the Cadence 6.1 and Calibre tools that we use.
- Delivering high quality layout that conforms to all design requirements.
- Full understanding of hierarchical planning (top down and bottom up) and integration

- Meet all tape out schedules
- Able to work in a large team environment
- Full self-sufficiency in debugging complex verification failures
- Able to work with an out shore team in India on a daily bases
- Able to used the Cadence 6.1 and 12.1 Virtuoso environment.
- Able to used the Calibre verification tools.
- Understanding 40nm, 28nm and 14nm FinFET processes

- 5 to 10 years experience in RF/analog layout
- Custom layout experience must include high frequency circuits such as LNAs, Mixers, VCOs, etc.
- Full familiarity with Cadence Virtuoso and Mentor Graphics Calibre tools
- 40nm, 28nm and 14nm FinFET design processes
- Outstanding written and verbal communication

Preferred Skills/Experience:
- Experience leading 10+ layout designers
- Chip level management from project inception through tape out
- 40nm, 28nm and 14nm FinFET and/or SOI processes
- Proficiency with Virtuoso IC6.1.6 and IC12.1
- Proficiency with design management tools such as Synchronicity
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