Soc Verification Engineer

Location: San Jose, CA
Date Posted: 10-07-2016
Our clients SoC/Digital ASIC Team is currently seeking candidates with experience in Verification of Coherent Bridge IP cores and subsystems, for large SoC devices.  Responsibilities will include design verification of IP cores using latest verification methodologies such as System Verilog , UVM. The engineer will develop test plans and influence the overall Verification strategy.

Design Verification of Coherent Bridge IP cores and subsystems using latest verification methodologies such as System Verilog, UVM. Develop Functional test plans for the various IP cores and subsystems. Develop constrained random verification tests and directed tests and ensure that functional coverage, code coverage and performance goals are met. Develop formal verification strategy, create properties and constraints for IP cores. Work with Architecture and Design Engineering teams and ensure that IP cores work as per the standard Perform gate level and back annotated timing simulations. Work closely with Design Engineering Team, Architects, Validation and Software teams and ensure robust verification of IP cores in a subsystems Assist in post silicon bring-up and debug. 8 -12 years of experience in ASIC/SoC Design Verification including, experience using latest Verification methodologies such as System Verilog, and UVM.

Experience with PCIE Express protocol is a must.
Experience with AMBA bus protocols especially CHI
Experience in system bus with QOS, cache coherent bus and bridge unit verification
Working knowledge in one or more of the following: C, C++, Python, TCL or Perl.
Experience in scripting for automation of design methodologies & flows

Direct and relevant experience with multi-CPU core SOC solutions ARMv8 processor architecture understanding and knowledge Broad experience in SoC development from design concept through silicon bring-up

Bachelor's, Electrical Engineering

Technical Recruiter
Novus Resources  

this job portal is powered by CATS