Digital Design Engineers for Mixed - Signal Power Management ASICs

Location: San Diego, CA
Date Posted: 12-15-2016
Seeking Digital Design Engineers for the mixed-signal ASICs that support QCTs mobile platforms including Radio Frequency (RFIC), Power Management (PMIC), and Codec devices. Successful candidates will be responsible for leading, and participating in, the design of leading edge ASICs in advanced digital CMOS processes for multi-function mobile platforms.

Design candidates will have a minimum of 5-10 years of relevant experience and must have detailed knowledge of digital ASIC design including architecture, RTL design for control and signal processing functions, Lint, CDC, synthesis, STA, and DFT. Design candidates must also have experience with leading-edge ASIC development tools from Synopsys, Mentor, or Cadence. Able to perform basic verification checks and work closely with Design Verification in order to ensure quality and completeness of test plans, successful functional coverage closure and ultimately first time right silicon.

Experience designing mixed signal interfaces and integrating digital modules into mixed-signal ASICs is desirable. Experience in low power design and implementation techniques is desirable.

Required: Bachelor's, Electrical Engineering
Preferred: Master's, Electrical Engineering or equivalent experience 
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