Design Verification Engineer - Digital IP Block Level Verification

Location: San Diego, CA
Date Posted: 01-10-2017
Digital IP block level verification for RFFE

We are seeking digital verification engineers for the mixed-signal ASICs that support mobile platforms for next generation 5G RFIC technologies. Successful candidates will be working on the following:
- Block level digital IP verification using constraint-random coverage methodologies at both RTL and Gate Level. The skills involved includes SV/UVM/UVM_REG/Randomization/Coverage/SVA.


-3 years minimum experience and working knowledge of Object-Oriented SystemVerilog principles using UVM/OVM/VMM methodologies.


- Extensive hands on experience in verifying digital blocks, building UVM based TB, writing UVM sequences, constraint-random testcases, using regModel (UVM_REG) API, drivers, monitors, scoreboard, functional coverage (covergroups), assertions (SVA), simulations, regression, debug, bug reporting/tracking.
-Experience in debugging RTL & Gate level simulations
-Part of multiple tapeouts with high quality verification.


Required: Bachelor's, Computer Engineering and/or Electrical Engineering
Preferred: Master's, Computer Engineering and/or Electrical Engineering
Technical Recruiter
Novus Resources
resumes@novus-resources.com  


 
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