Digital Verification Engineer

Location: San Diego, CA
Date Posted: 01-11-2017
Currently seeking digital verification engineers for the mixed-signal ASICs that support mobile platforms for next generation RFIC/PMIC/Codec technologies. Successful candidates will be working on the following: - Block/Subsystem/SoC level digital IP verification using constraint-random coverage methodologies at both RTL and Gate Level. The skills involved includes SV/UVM/UVM_REG/Randomization/Coverage/SVA.

-Minimum Bachelors degree in Electrical Engineering or Computer Engineering - 3years minimum experience and working knowledge of Object-Oriented SystemVerilog principles using UVM/OVM/VMM methodologies.

- Extensive hand on experience in verifying digital blocks, building UVM based TB, writing UVM sequences, constraint-random testcases, using regModel (UVM_REG) API, drivers, monitors, scoreboard, functional coverage (covergroups), assertions (SVA), simulations, regression, debug, bug reporting/tracking. -Experience in debugging RTL & Gate level simulations -Part of multiple tapeouts with high quality verification.

Required: Bachelor's, Electrical Engineering Preferred: Master's, Electrical Engineering or equivalent experience
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