BigBox Emulation/Methodology Engineer

Location: San Diego, CA
Date Posted: 02-09-2017
Novus' customer is looking for someone to join their team that is part of the central SoC digital hardware organization responsible for the overall quality of the SoC silicon. The SVE team works closely with architects, designers, verification engineers, software engineers, and customers. As a member of the SVE methodology team you will be involved in developing the methodology architectural components and contribute directly to technical aspects of the simulation acceleration using SVTB/OVM methodology(Veloce/Palladium). You will work closely with cross-functional teams such as design and CAD by leveraging domain-specific expertise, sharing, and coordinating prototyping efforts, testing and support. You will also be responsible for developing, implementing and deploying advanced emulation methodology across all chips and IP cores/blocks, development of reusable testbench platforms and environments that cut across simulation, simulation acceleration, emulation and post silicon validation.


Candidates should possess experience in the build and bring up of complex SOCs on emulation platforms (Veloce/Palladium/Zebu/Custom Xilinx platforms). Exceptional troubleshooting skills is a must. Experience with ARM processors and AMBA protocols. Good programming logic (C/C++). Good understanding of RTL (System Verilog for design). Enabling new emulation/simxl methodologies and documenting.


Gate Level Emulation/Scan dump/DFT/UPF on big boxes. Experience with UVM, DPI-C. Performance and Power estimation using emulation. Understanding of Jtag/CMM scripts/Trace32. Scripting (Perl/TCL) . Peripherals (DDR/USB/UFS) emulation/bringup. Understanding of different simulation tools/environments (Questa/VCS/Incisive).


Required: Bachelor's, Electrical Engineering Preferred: Master's, Electrical Engineering or equivalent experience
Technical Recruiter
Novus Resources
resumes@novus-resources.com  


 
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