SoC Design and Verification Engineer for Low Power

Location: Tempe, AZ
Date Posted: 03-19-2017
 Seeking engineer with knowledge of sub-micron SoC technologies that require power domain definition and low power verification. For low power SoCs, power domains are defined using UPF which is must be validated through a multiple step verification process. Seeking a candidate who can perform this low power verification using SoC design tools.

3 years of applicable work experience in low power verification. This includes understanding power domain definition through UPF or CPF, functional and power intent equivalency checking and verification through power aware System Verilog simulation. Familiar with low power SoC design constructs such as clock gates, level shifters, isolation cells and state retention cells.

Preferred candidates would have experience using Cadence Conformal Low Power verification and performing analysis of results.

Required: Bachelor's, Computer Engineering and/or Electrical Engineering
Technical Recruiter
Novus Resources  

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