FPGA and RTL Integration Engineer

Location: San Diego, CA
Date Posted: 04-06-2017
Novus is looking for a dedicated engineer to perform the following:

- RTL IP integration
- Perform full system simulation
- Map a new SOC design to a Xilinx FPGA platform (MCU, AHB, memory, custom logic)
- FPGA Constraints, Synthesis, P&R, Floorplanning, Timing Closure
- Low Power digital design
- Provide lab support throughout project

- FPGA experience
- Xilinx, Vivado development suite
- Verilog, SV, C code, UVM
- ASIC flows: Synthesis, PLDRC, FV, CDC
- Excellent Technical Communications Skills (both written and verbal)
- Ability to work in a Team Environment
- Self Direction and Strong Time Management Skills

- MS degree, 7+ years (ideally 5-10 years experience)
- Clearcase

- BS/MS degree in EE/CS
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