Validation Power Content Development Engineer

Location: San Diego, CA
Date Posted: 08-03-2017
Novus' customer is currently seeking a candidate for the position of System and CPU/SOC Power Validation Engineer. In this role you will work with a local and global team to understand, implement and verify the power features, power savings, power saving predictions, and performance of implementations of current and next-generation SoCs. You will create and execute test plans in both emulation and Post-Si environments, and work to discover, root-cause and correct failures in hardware and software. Additionally, you will create the software and flows which allow the maximum use of power saving features.

Candidate will have a minimum of 3 years of experience working in power estimate tools, emulation and silicon environments. Candidates are expected to have experience in:
-Emulation environments for hardware and software development and debug
-Familiarity with Power Estimate software such as Ansys, Cadence, and Primetime tools
-Analyzing power estimates, correlation, and power efficiency
-Verilog RTL
-CPU and SoC architectures
-Strong C programming skills
-Strong understanding of power and performance features
-Understanding of silicon features such as isolation, clock gating, and power gating methodologies
-Basic understanding of debug

-Strong power background for pre and post silicon environments
-Strong Python/Perl scripting experience, including tool creation and flow automation
- Implementing bare-metal drivers and test content
-Experience in low level C drivers, micro kernel, RTOS, Linux, etc.
-Analyzing power data and drawing conclusions compared to pre-silicon

Required: Bachelor's, Electrical Engineering
Preferred: Master's, Electrical Engineering or equivalent experience
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