Junior DFT Engineer

Location: San Diego, CA
Date Posted: 08-04-2017
Our client's Digital ASIC Design Team is currently seeking a candidate for a junior position responsible for the implementation of advanced DFT/DFD(design for test/design for debug) techniques for low power, high performance and highly integrated SoCs including CODEC and high-speed PHY & SerDes systems. The successful candidate will help in the deployment of DFT methodologies that reduce test cost, increase production quality and enhance yield learning. Deployment and implementation of advanced DFT/DFD(design for test/design for debug) techniques for low power, high performance and highly integrated SoCs including CODEC and high-speed PHY & SerDes systems. Deployment of DFT methodologies that reduce test cost, increase production quality and enhance yield learning.


- Strong fundamental knowledge of DFT/DFD techniques for high performance processors.
- Understanding of core-based test methodology and scan isolation.
- Knowledge in fault modeling Stuck-at, Transition, Path Delay, Gate-Exhaustive, IDDQ, and other advanced DFT models.
- Knowledge in JTAG, MBIST, Scan Compression, ATPG, Fault Simulation and at-speed testing.
- Experience with industry ATPG tools Synopsys Tetramax, Cadence Encounter Test or Mentor Fastscan ATPG tools.
- Synopsys DFTC scan insertion.
- Experience in Logic Design, VHDL, Verilog RTL, verification, and static timing analysis.


2-4 years of industry experience


Required: Bachelor's, Electrical Engineering
Preferred: Master's
 
Technical Recruiter
Novus Resources
resumes@novus-resources.com  


 
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