Digital Design Engineer

Location: San Jose, CA
Date Posted: 08-08-2017
Our client's digital ASIC team delivers cutting edge hardware and software products across every established wireless connectivity technology. They are currently seeking talented candidates for synthesis, static timing analysis, formal verification and timing closure of next-generation Wireless LAN devices.

Experience in ASIC Synthesis, STA, Timing closure and formal verification. Background in the synthesis and timing closure of large designs with multiple clock domains. Static timing closure experience for tapeout signoff. Formal verification experience for complex ECOs.

Experience with WiFi is highly desirable

Requiered: Bachelor's, Electrical Engineering
Preferred: Master's, Electrical Engineering
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