Design Verification Engineer

Location: Raleigh, NC
Date Posted: 08-11-2017
Novus' client's server division has a position available for a Design Verification Engineer. This team is responsible for developing transactors for bus protocols, and design verification for several high speed configurable bus designs. Teams members are responsible for developing design corresponding test plans, architecting and developing verification environments, verification of complex designs until coverage goals are achieved dynamically or statically, and completing all required verification activities at IP.

Required Experience
2+ years of experience are required in the following areas:
  • Industry experience in a Design Verification role
  • Hardware verification languages (HVL) such as SystemVerilog testbench (OVM/UVM), SystemC, or custom in house methodologies
  • Hardware description languages (HDL) such as Verilog, SystemVerilog or VHDL
  • Analytic and debugging skills - Understanding of Object Oriented Programming (OOP) concepts
  • Understanding of digital design
  • Excellent communication and team work skills experience with cache coherence
Industry experience: cache, coherence, AMBA, AXI, ACE, CHI, System Verilog, UVM, OVM, specman, vera
 
Required:
Bachelor's, Computer Engineering and/or Computer Science and/or Electrical Engineering
 
Technical Recruiter
Novus Resources
resumes@novus-resources.com  


 
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