Verification Engineer

Location: Austin, TX
Date Posted: 08-29-2017
Novus is seeking Verification Engineers to do subsystem cache coherent bus.  Candidates will be developing transactors for bus protocols, as well as design verification for several high speed configurable bus designs. Candidates will be involved and contributing to the test plans, developing test-bench until coverage goals are achieved dynamically or statically, and completing all required verification activities at IP level as well as subsystem level. 
Qualifications:  
  • 5+ years of industry experience in a Design Verification role 
  • Hardware verification languages (HVL) such as SystemVerilog testbench (OVM/UVM), SystemC, or custom in house methodologies 
  • Hardware description languages (HDL) such as Verilog, SystemVerilog or VHDL 
  • Analytic and debugging skills - Understanding of Object Oriented Programming (OOP) concepts 
  • Understanding of digital design. expertise and with cache coherence.
Technical Recruiter
Novus Resources
resumes@novus-resources.com  


 
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