Synthesis/Formal Equivalency Engineer

Location: Raleigh, NC
Date Posted: 09-01-2017
Our client's Digital ASIC Design Team is currently seeking candidates with chip design and I/P integration experience to be involved with SoC creation for advanced multi-CPU core designs. The Design/SoC Synthesis Engineer will work with internal and external I/P blocks, subsystems and RTL logic - with responsibilities for logic synthesis, formal equivalency and design checking tools. -Run Synthesis, LINT checking and Clock-Domain checking tools -Run Formal Equivalency checking -Work with Physical design team for complete design performance achievement including timing closure assistance.

-3+ years of experience in ASIC/SoC Design and Integration
-Working knowledge in one or more of the following: TCL or Perl.
-Formal Verification experience desired.
-Knowledge of high performance processors and large complex SOCs
-Solid background in scripting for automation of design methodologies & flows
-Ultra low-power design practices/implementation
-Detail oriented with strong organizational, problem solving, and communication skills (both written and oral)
-Strong understanding of chip integration procedures, methodologies & flows
-Ability to work in a team environment

-Experience in Logic Design, VHDL, Verilog & SystemVerilog RTL, synthesis, LINT, Formal Verification, and static timing analysis, clock domain crossing techniques/implementation

Required: Bachelor's, Electrical Engineering or equivalent experience
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